The present invention generally relates to a semiconductor device and more particularly to a semiconductor device suited for implementing a high-speed logic circuit of low power consumption with an increased packing density.
In hitherto known LSI devices, attempts have been made to decrease the device area by merging a bipolar transistor with an MOS FET in such a structure in which the base of the bipolar transistor is used commonly as the source or drain of the MOS FET, as disclosed, for example, in JP-A-No. 48-39175. With such merged or composite structure, the bipolar transistor and the MOS FET cooperates to form a PNPN device as a parasitic element. This PNPN device has a tendency to be turned on in dependence on the operating conditions to cause a so-called latch-up phenomenon to take place, which a problem in practical applications.
The present inventors have attempted to analytically understand the latch-up phenomenon by using a circuit composed of bipolar transistors and MOS FETs connected in such an arrangement as shown in FIGS. 1 and 2 of the accompanying drawings.
In this conjunction, it should be mentioned that the circuit configuration shown in FIG. 1 of the accompanying drawings is substantially the same as the one shown in FIG. 1 of JP-A-No. 59-8431 which was invented through cooperation of one of the present inventors with other persons except that a resistor 121 is present in the case of the circuit shown in FIG. 1 of the accompanying drawings. This resistor has an important relationship to the latch-up phenomenon, as will be elucidated below.
As the result of the analytical study conducted by the present inventors, it has been found that the portion in which the latch-up takes places in the circuit shown in FIG. 1 lies in a region covered by a bipolar transistor 110 and an FET 105. More specifically, it is assumed that a PNPN device (which corresponds to the one constituted by the layers 227, 225, 226 and 229 shown in FIG. 2) formed between the bipolar transistor 110 and the source region 227 of the FET 105 is turned on under certain conditions of operation. The PNPN device once turned on will continue to be in the conducting state. At that time, the current flowing through the PNPN device continues to increase until the current is limited by the resistor 121. In this state, the source region 227 of the FET 105 is constantly applied with a voltage in the forward direction relative to the collector 222 of the bipolar transistor 110. Under these conditions, no effective means is available to interrupt the conduction of the PNPN device except for decreasing the supply voltage to an extremely low level. This is the phenomenon referred to as the latch-up.